Wafer bonding of some semiconductor materials to a silicon substrate can be problematic for a number of reasons. Differences in thermal expansion coefficients and lattice mismatches are among the reasons for such difficulties in wafer bonding.
One layer transfer wafer bonding process that has been employed for some applications is known as the SmartCut® process. The process involves the implantation of ions within a monocrystalline silicon wafer. The ions, typically hydrogen ions (H+), form a layer of microbubbles parallel to the wafer surface that later functions as a cleavage plane. U.S. Pat. No. 5,374,564, which is incorporated by reference herein, discloses such a process. As discussed in U.S. Pat. No. 5,882,987, also incorporated by reference herein, an oxide layer is thermally grown on the device wafer surface prior to ion implantation during the SmartCut® fabrication process. The device wafer is bonded to a silicon handle wafer, after which annealing steps are conducted. The device wafer is fractured along the hydride rich plane. The exposed surface following such fracture is polished, for example by chemical mechanical polishing (CMP), to obtain a smooth surface. U.S. Pat. No. 6,326,285, also incorporated by reference herein, discloses techniques for silicon on insulator fabrication, including hydrogen implantation, wafer bonding, and cleaving along the hydrogen layer.
Many applications benefit from the use of semiconductor materials other than silicon. Device layers comprising III-V semiconductor materials may, for example, be grown on germanium substrates. II-VI semiconductor materials are also employed in some applications as device layers. Some semiconductor materials are not available as bulk structures as their mechanical properties (e.g. weight, brittleness) do not facilitate such use.